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Clock signal
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#	Item
241	SLG84450B Clock Synthesizer for Intel mobile PCI Express Chipset Features Output Summary Add to Reading List Source URL: www.silego.com Language: English - Date: 2010-03-05 13:51:16 Electronics Digital electronics Conventional PCI PCI Express Phase-locked loop Flip-flop Clock signal Bus PC/104 Computer hardware Electronic engineering Computer buses
242	SLG8UM610 Low Power Clock Synthesizer for Intel UMPC Systems Features Output Summary Add to Reading List Source URL: www.silego.com Language: English - Date: 2010-03-05 13:49:45 Computer hardware Computer memory Computer buses Oscillators Phase-locked loop Central processing unit Low-voltage differential signaling Flip-flop Clock signal Electronic engineering Electronics Digital electronics
243	1. Introduction The work described in this report continues similar work described in a previous report [3]. That report describes a software program that implements an optimal linear demodulator and decoder for direct-p Add to Reading List Source URL: www.eecis.udel.edu Language: English - Date: 1998-07-29 12:41:32 Time in the United States Electromagnetism Digital signal processing Electronic circuits Horology WWV Radio clock Analog-to-digital converter Modulation Electronics Electronic engineering National Institute of Standards and Technology
244	SLG8LP465 Low Power Clock Synthesizer for Intel mobile PCI Express Features Output Summary Add to Reading List Source URL: www.silego.com Language: English - Date: 2010-03-05 13:51:05 Computer buses Digital electronics Electronic design Conventional PCI PCI Express Flip-flop Phase-locked loop Clock signal Bus Electronic engineering Computer hardware Electronics
245	KineticSystems CAMAC Programmable Clock Generator Module Data Sheet[removed] Add to Reading List Source URL: www.kscorp.com Language: English - Date: 2013-05-16 14:28:02 Physics Clock signal Clock generator Electronic test equipment Electronic circuits Electronics Electronic engineering Computer Automated Measurement and Control
246	Optimal Gradient Clock Synchronization in Dynamic Networks Fabian Kuhn Christoph Lenzen Add to Reading List Source URL: distcomp.ethz.ch Language: English - Date: 2010-07-29 05:34:11 Theoretical computer science Synchronization Network theory Clock signal Clock skew Flow network Connectivity Shortest path problem Clock synchronization Graph theory Mathematics Network flow
247	Optimal Dynamic Gradient Clock Synchronization Fabian Kuhn Christoph Lenzen Thomas Locher Add to Reading List Source URL: distcomp.ethz.ch Language: English - Date: 2010-07-30 08:11:15 Clock signal Locher Clock synchronization Clocks Synchronization
248	Gradient Clock Synchronization in Dynamic Networks Fabian Kuhn Thomas Locher Rotem Oshman Add to Reading List Source URL: distcomp.ethz.ch Language: English - Date: 2009-07-23 06:32:35 Clock skew Flow network Bridge Symplectic geometry Skew-symmetric graph Push-relabel maximum flow algorithm Graph theory Network flow Clock signal
249	PowerLeap® PL-AXP™ Quick Start Guide Thank you for purchasing the PowerLeap PL-AXP™. The PL-AXP allows you to (1) Upgrade older AMD Athlon/Duron CPUs (Socket 462, aka Socket A) to the modern AMD Athlon XP Add to Reading List Source URL: www.powerleap.com Language: English - Date: 2008-10-27 21:23:18 Socket A Advanced Micro Devices Front-side bus Duron CPU multiplier Pentium III Athlon 64 Computer hardware Clock signal Athlon
250	INSTRUMENTS, INC. Frequency and Phase Agile 120MHz Signal Generator Module Model DDS8p Add to Reading List Source URL: www.novatech-instr.com Language: English - Date: 2003-07-02 21:16:03 Crystal oscillator Electronics Technology Electronic engineering Oscillators Clock signal RS-232

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